The present invention relates to a semiconductor integrated circuit device and a method of operating it, and principally to a technique effective for use in a digital integrated circuit device such as a dynamic RAM (Random Access Memory) comprising CMOS circuits each composed of low threshold-voltage type MOSFETs and in a method of operating the digital integrated circuit device.
MOSFETs experience reduced withstand voltage with increased micronization. It is therefore necessary to reduce the operating voltage of a circuit composed of the MOSFETs shaped in micro form. Since a gate voltage supplied to the gate of each MOSFET is also lowered in this case, it is necessary to reduce the threshold voltage of the MOSFET so that even the lowered gate voltage provides for flow of a desired current. However, when the threshold voltage is reduced, a leakage current (hereinafter called a "subthreshold leakage current"), which flows when each MOSFET is brought into an off state, in which the gate and source thereof are equal in voltage to each other, increases exponentially. Thus, even in the case of a CMOS circuit, current consumption at the time of its deactivation increases.
A circuit for reducing the subthreshold leakage current referred to above has been disclosed in Japanese Patent Application Laid-Open Nos. 6(1994)-237164 and 8(1996)-83487 and U.S. Pat. Nos. 5,274,601 and 5,408,144 by way of illustrative example. As a method of reducing the leakage current using such a circuit, a CMOS inverter circuit wherein at the time that an input thereof received during its non-operation and an output thereof have been determined as a high level and a low level, respectively, will be described by way of example. In this case, a P channel MOSFET of the CMOS inverter circuit is in an off state and an N channel MOSFET thereof is in an on state. A leakage current produced in the CMOS inverter circuit is determined depending on the subthreshold leakage current of the turned-off P channel MOSFET.
A P channel power switch MOSFET is provided between an operating voltage node connected to the source of the P channel MOSFET of the CMOS inverter circuit and a power line and is turned off upon non-operation. In doing so, the potential at each internal power line placed in a floating state is reduced by the subthreshold leakage current. When the potential is reduced to a some extent, a reverse bias voltage is applied between the gate and source of the P channel MOSFET of the CMOS circuit so that the subthreshold leakage current can be substantially eliminated.